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dc.contributor.authorHammond, Kevin
dc.contributor.authorBrown, Christopher Mark
dc.contributor.authorSarkar, Susmit
dc.contributor.editorvan Eekelen, Marko
dc.contributor.editorDal Lago, Ugo
dc.date.accessioned2016-12-05T12:30:29Z
dc.date.available2016-12-05T12:30:29Z
dc.date.issued2016
dc.identifier.citationHammond , K , Brown , C M & Sarkar , S 2016 , Timing properties and correctness for structured parallel programs on x86-64 multicores . in M van Eekelen & U Dal Lago (eds) , Foundational and Practical Aspects of Resource Analysis : 4th International Workshop, FOPARA 2015, London, UK, April 11, 2015. Revised Selected Papers . Lecture Notes in Computer Science , vol. 9964 , Springer , pp. 101-125 , 4th International Workshop, Foundational and Practical Aspects of Resource Analysis (FOPARA 2015) , London , United Kingdom , 11/04/15 . https://doi.org/10.1007/978-3-319-46559-3_6en
dc.identifier.citationworkshopen
dc.identifier.isbn9783319465586
dc.identifier.isbn9783319465593
dc.identifier.issn0302-9743
dc.identifier.otherPURE: 248130167
dc.identifier.otherPURE UUID: 6e70a1de-b0e5-44e1-a788-5ceb09100b7f
dc.identifier.otherScopus: 85007564192
dc.identifier.otherORCID: /0000-0002-4326-4562/work/33080443
dc.identifier.otherORCID: /0000-0001-6030-2885/work/70619194
dc.identifier.otherORCID: /0000-0002-4259-9213/work/125727585
dc.identifier.urihttps://hdl.handle.net/10023/9935
dc.description.abstractThis paper determines correctness and timing properties for structured parallel programs on x86-64 multicores. Multicore architectures are increasingly common, but real architectures have unpredictable timing properties, and even correctness is not obvious above the relaxed-memory concurrency models that are enforced by commonly-used hardware. This paper takes a rigorous approach to correctness and timing properties, examining common locking protocols from first principles, and extending this through queues to structured parallel constructs. We prove functional correctness and derive simple timing models, and both extend for the first time from low-level primitives to high-level parallel patterns. Our derived high-level timing models for structured parallel programs allow us to accurately predict upper bounds on program execution times on x86-64 multicores.
dc.format.extent26
dc.language.isoeng
dc.publisherSpringer
dc.relation.ispartofFoundational and Practical Aspects of Resource Analysisen
dc.relation.ispartofseriesLecture Notes in Computer Scienceen
dc.rights© 2016, Springer International Switzerland. This work has been made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at link.springer.com / https://doi.org/ 10.1007/978-3-319-46559-3 6en
dc.subjectMulticoreen
dc.subjectRelaxed-memory concurrencyen
dc.subjectFunctional correctnessen
dc.subjectAlgorithmic skeletonsen
dc.subjectOperational semanticsen
dc.subjectTiming modelsen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectQA76 Computer softwareen
dc.subjectTA Engineering (General). Civil engineering (General)en
dc.subjectDASen
dc.subject.lccQA75en
dc.subject.lccQA76en
dc.subject.lccTAen
dc.titleTiming properties and correctness for structured parallel programs on x86-64 multicoresen
dc.typeConference itemen
dc.contributor.sponsorEuropean Commissionen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen
dc.contributor.institutionUniversity of St Andrews. Centre for Interdisciplinary Research in Computational Algebraen
dc.identifier.doihttps://doi.org/10.1007/978-3-319-46559-3_6
dc.date.embargoedUntil2016-12-04
dc.identifier.grantnumber644235en


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