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Mapping parallel programs to heterogeneous CPU/GPU architectures using a Monte Carlo Tree Search
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dc.contributor.author | Goli, Mehdi | |
dc.contributor.author | McCall, John | |
dc.contributor.author | Brown, Christopher Mark | |
dc.contributor.author | Janjic, Vladimir | |
dc.contributor.author | Hammond, Kevin | |
dc.date.accessioned | 2015-03-03T11:31:05Z | |
dc.date.available | 2015-03-03T11:31:05Z | |
dc.date.issued | 2013-06-20 | |
dc.identifier | 51070558 | |
dc.identifier | 8ee5d875-a11f-462c-b0f7-672d81284a62 | |
dc.identifier | 84881588847 | |
dc.identifier.citation | Goli , M , McCall , J , Brown , C M , Janjic , V & Hammond , K 2013 , Mapping parallel programs to heterogeneous CPU/GPU architectures using a Monte Carlo Tree Search . in 2013 IEEE Congress on Evolutionary Computation, CEC 2013 . IEEE , pp. 2932-2939 . https://doi.org/10.1109/CEC.2013.6557926 | en |
dc.identifier.isbn | 9781479904532 | |
dc.identifier.isbn | 9781479904525 | |
dc.identifier.other | ORCID: /0000-0002-4326-4562/work/33080456 | |
dc.identifier.other | ORCID: /0000-0001-6030-2885/work/70619184 | |
dc.identifier.uri | https://hdl.handle.net/10023/6157 | |
dc.description.abstract | The single core processor, which has dominated for over 30 years, is now obsolete with recent trends increasing towards parallel systems, demanding a huge shift in programming techniques and practices. Moreover, we are rapidly moving towards an age where almost all programming will be targeting parallel systems. Parallel hardware is rapidly evolving, with large heterogeneous systems, typically comprising a mixture of CPUs and GPUs, becoming the mainstream. Additionally, with this increasing heterogeneity comes increasing complexity: not only does the programmer have to worry about where and how to express the parallelism, they must also express an efficient mapping of resources to the available system. This generally requires in-depth expert knowledge that most application programmers do not have. In this paper we describe a new technique that derives, automatically, optimal mappings for an application onto a heterogeneous architecture, using a Monte Carlo Tree Search algorithm. Our technique exploits high-level design patterns, targeting a set of well-specified parallel skeletons. We demonstrate that our MCTS on a convolution example obtained speedups that are within 5% of the speedups achieved by a hand-tuned version of the same application. | |
dc.format.extent | 8 | |
dc.format.extent | 812021 | |
dc.language.iso | eng | |
dc.publisher | IEEE | |
dc.relation.ispartof | 2013 IEEE Congress on Evolutionary Computation, CEC 2013 | en |
dc.rights | © © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. | en |
dc.subject | Monte Carlo Tree Search | en |
dc.subject | Heuristic algorithm | en |
dc.subject | Static mapping | en |
dc.subject | Parallel programming | en |
dc.subject | Heterogenous architecture | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject.lcc | QA75 | en |
dc.title | Mapping parallel programs to heterogeneous CPU/GPU architectures using a Monte Carlo Tree Search | en |
dc.type | Conference item | en |
dc.contributor.sponsor | European Commission | en |
dc.contributor.sponsor | European Commission | en |
dc.contributor.sponsor | EPSRC | en |
dc.contributor.sponsor | EPSRC | en |
dc.contributor.institution | University of St Andrews.School of Computer Science | en |
dc.contributor.institution | University of St Andrews.Centre for Interdisciplinary Research in Computational Algebra | en |
dc.identifier.doi | 10.1109/CEC.2013.6557926 | |
dc.identifier.grantnumber | n/a | en |
dc.identifier.grantnumber | FP&-ICT-2011-7 | en |
dc.identifier.grantnumber | EP/G055181/1 | en |
dc.identifier.grantnumber | EP/F030657/1 | en |
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