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dc.contributor.authorBanks, Christopher
dc.contributor.authorElver, Marco
dc.contributor.authorHoffmann, Ruth
dc.contributor.authorSarkar, Susmit
dc.contributor.authorJackson, Paul
dc.contributor.authorNagarajan, Vijay
dc.contributor.editorStewart, Daryl
dc.contributor.editorWeissenbacher, Georg
dc.date.accessioned2017-10-17T15:30:08Z
dc.date.available2017-10-17T15:30:08Z
dc.date.issued2017-10-02
dc.identifier.citationBanks , C , Elver , M , Hoffmann , R , Sarkar , S , Jackson , P & Nagarajan , V 2017 , Verification of a lazy cache coherence protocol against a weak memory model . in D Stewart & G Weissenbacher (eds) , Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) . FMCAD Inc , pp. 60-67 , Formal Methods in Computer-Aided Design (FMCAD) , Vienna , Austria , 2/10/17 . < https://dl.acm.org/citation.cfm?id=3168470 >en
dc.identifier.citationconferenceen
dc.identifier.isbn9780983567875
dc.identifier.otherPURE: 250534181
dc.identifier.otherPURE UUID: e54b2d29-a2cd-4588-864d-32a0b5dbcd41
dc.identifier.otherScopus: 85044646755
dc.identifier.otherORCID: /0000-0002-1011-5894/work/37898079
dc.identifier.otherWOS: 000433173000015
dc.identifier.otherORCID: /0000-0002-4259-9213/work/125727597
dc.identifier.urihttps://hdl.handle.net/10023/11870
dc.descriptionFunding: EPSRC grant EP/M027317/1en
dc.description.abstractIn this paper, we verify a modern lazy cache coherence protocol, TSO-CC, against the memory consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a novel finite-state operational model which exhibits the laziness of TSO-CC and satisfies TSO. We then extend this by an existing parameterisation technique, allowing verification for an unbounded number of processors. The approach is executed entirely within a model checker, no external tool is required and very little in-depth knowledge of formal verification methods is required of the verifier.
dc.language.isoeng
dc.publisherFMCAD Inc
dc.relation.ispartofProceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)en
dc.rightsCopyright © 2017, the Author(s) and FMCAD Inc. This work has been made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version.en
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectT-NDASen
dc.subjectBDCen
dc.subject.lccQA75en
dc.titleVerification of a lazy cache coherence protocol against a weak memory modelen
dc.typeConference itemen
dc.contributor.sponsorEPSRCen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen
dc.identifier.urlhttps://dl.acm.org/citation.cfm?id=3168470en
dc.identifier.grantnumberEP/M027317/1en


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