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Verification of a lazy cache coherence protocol against a weak memory model
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dc.contributor.author | Banks, Christopher | |
dc.contributor.author | Elver, Marco | |
dc.contributor.author | Hoffmann, Ruth | |
dc.contributor.author | Sarkar, Susmit | |
dc.contributor.author | Jackson, Paul | |
dc.contributor.author | Nagarajan, Vijay | |
dc.contributor.editor | Stewart, Daryl | |
dc.contributor.editor | Weissenbacher, Georg | |
dc.date.accessioned | 2017-10-17T15:30:08Z | |
dc.date.available | 2017-10-17T15:30:08Z | |
dc.date.issued | 2017-10-02 | |
dc.identifier | 250534181 | |
dc.identifier | e54b2d29-a2cd-4588-864d-32a0b5dbcd41 | |
dc.identifier | 85044646755 | |
dc.identifier | 000433173000015 | |
dc.identifier.citation | Banks , C , Elver , M , Hoffmann , R , Sarkar , S , Jackson , P & Nagarajan , V 2017 , Verification of a lazy cache coherence protocol against a weak memory model . in D Stewart & G Weissenbacher (eds) , Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) . FMCAD Inc , pp. 60-67 , Formal Methods in Computer-Aided Design (FMCAD) , Vienna , Austria , 2/10/17 . < https://dl.acm.org/citation.cfm?id=3168470 > | en |
dc.identifier.citation | conference | en |
dc.identifier.isbn | 9780983567875 | |
dc.identifier.other | ORCID: /0000-0002-1011-5894/work/37898079 | |
dc.identifier.other | ORCID: /0000-0002-4259-9213/work/125727597 | |
dc.identifier.uri | https://hdl.handle.net/10023/11870 | |
dc.description | Funding: EPSRC grant EP/M027317/1 | en |
dc.description.abstract | In this paper, we verify a modern lazy cache coherence protocol, TSO-CC, against the memory consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a novel finite-state operational model which exhibits the laziness of TSO-CC and satisfies TSO. We then extend this by an existing parameterisation technique, allowing verification for an unbounded number of processors. The approach is executed entirely within a model checker, no external tool is required and very little in-depth knowledge of formal verification methods is required of the verifier. | |
dc.format.extent | 297521 | |
dc.language.iso | eng | |
dc.publisher | FMCAD Inc | |
dc.relation.ispartof | Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject | T-NDAS | en |
dc.subject | BDC | en |
dc.subject.lcc | QA75 | en |
dc.title | Verification of a lazy cache coherence protocol against a weak memory model | en |
dc.type | Conference item | en |
dc.contributor.sponsor | EPSRC | en |
dc.contributor.institution | University of St Andrews. School of Computer Science | en |
dc.identifier.url | https://dl.acm.org/citation.cfm?id=3168470 | en |
dc.identifier.grantnumber | EP/M027317/1 | en |
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