Verification of a lazy cache coherence protocol against a weak memory model
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In this paper, we verify a modern lazy cache coherence protocol, TSO-CC, against the memory consistency model it was designed for, TSO. We achieve this by first showing a weak simulation relation between TSO-CC (with a fixed number of processors) and a novel finite-state operational model which exhibits the laziness of TSO-CC and satisfies TSO. We then extend this by an existing parameterisation technique, allowing verification for an unbounded number of processors. The approach is executed entirely within a model checker, no external tool is required and very little in-depth knowledge of formal verification methods is required of the verifier.
Banks , C , Elver , M , Hoffmann , R , Sarkar , S , Jackson , P & Nagarajan , V 2017 , Verification of a lazy cache coherence protocol against a weak memory model . in D Stewart & G Weissenbacher (eds) , Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) . FMCAD Inc , pp. 60-67 , Formal Methods in Computer-Aided Design (FMCAD) , Vienna , Austria , 2/10/17 . < https://dl.acm.org/citation.cfm?id=3168470 >conference
Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017)
Copyright © 2017, the Author(s) and FMCAD Inc. This work has been made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version.
DescriptionFunding: EPSRC grant EP/M027317/1
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