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dc.contributor.authorFlur, Shaked
dc.contributor.authorSarkar, Susmit
dc.contributor.authorPulte, Christopher
dc.contributor.authorNienhuis, Kyndylan
dc.contributor.authorMaranget, Luc
dc.contributor.authorGray, Kathryn
dc.contributor.authorSezgin, Ali
dc.contributor.authorBatty, Mark
dc.contributor.authorSewell, Peter
dc.contributor.editorFluet, Matthew
dc.date.accessioned2016-11-29T13:30:15Z
dc.date.available2016-11-29T13:30:15Z
dc.date.issued2017-01-01
dc.identifier246489959
dc.identifier5cf34b09-afc3-4c1c-81dd-6cd0e11694ad
dc.identifier85015336238
dc.identifier000408311200033
dc.identifier.citationFlur , S , Sarkar , S , Pulte , C , Nienhuis , K , Maranget , L , Gray , K , Sezgin , A , Batty , M & Sewell , P 2017 , Mixed-size concurrency : ARM, POWER, C/C++11, and SC . in M Fluet (ed.) , Proceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages (POPL 2017) . ACM SIGPLAN Notices , no. 1 , vol. 52 , ACM , New York , pp. 429-442 , POPL'17 44th ACM SIGPLAN Symposium on Principles of Programming Languages , Paris , France , 15/01/17 . https://doi.org/10.1145/3009837.3009839en
dc.identifier.citationconferenceen
dc.identifier.isbn9781450346603
dc.identifier.issn0362-1340
dc.identifier.otherORCID: /0000-0002-4259-9213/work/125727587
dc.identifier.urihttps://hdl.handle.net/10023/9901
dc.descriptionThis work was partly funded by the EPSRC Programme Grant REMS: Rigorous Engineering for Mainstream Systems, EP/K008528/1, EPSRC grant C3: Scalable & Verified Shared Memory via Consistency-directed Cache Coherence EP/M027317/1 (Sarkar), an ARM iCASE award (Pulte), a Gates Cambridge Scholarship (Nienhuis). and ANR grant WMC (ANR-11-JS02-011, Maranget).en
dc.description.abstractPrevious work on the semantics of relaxed shared-memory concurrency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and (to some degree) exposed at the C/C++ language level. A semantic foundation for software, therefore, has to address them. We investigate the mixed-size behaviour of ARMv8 and IBM POWER architectures and implementations: by experiment, by developing semantic models, by testing the correspondence between these, and by discussion with ARM and IBM staff. This turns out to be surprisingly subtle, and on the way we have to revisit the fundamental concepts of coherence and sequential consistency, which change in this setting. In particular, we show that adding a memory barrier between each instruction does not restore sequential consistency. We go on to extend the C/C++11 model to support non-atomic mixed-size memory accesses. This is a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.
dc.format.extent14
dc.format.extent335322
dc.language.isoeng
dc.publisherACM
dc.relation.ispartofProceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages (POPL 2017)en
dc.relation.ispartofseriesACM SIGPLAN Noticesen
dc.subjectRelaxed Memory Modelsen
dc.subjectMixed-sizeen
dc.subjectSemanticsen
dc.subjectISAen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectNDASen
dc.subjectBDCen
dc.subjectR2Cen
dc.subject~DC~en
dc.subject.lccQA75en
dc.titleMixed-size concurrency : ARM, POWER, C/C++11, and SCen
dc.typeConference itemen
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen
dc.identifier.doi10.1145/3009837.3009839


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