Mixed-size Concurrency: ARM, POWER, C/C++11, and SC
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Previous work on the semantics of relaxed shared-memory concurrency has only considered the case in which each load reads the data of exactly one store. In practice, however, multiprocessors support mixed-size accesses, and these are used by systems software and(to some degree) exposed at the C/C++ language level. A semantic foundation for software therefore has to address them.We investigate the mixed-size behaviour of ARMv8 and IBM POWER architectures and implementations: by experiment, by developing semantic models, by testing the correspondence between these, and by discussion with ARM and IBM staff. This turns out to be surprisingly subtle, and on the way we have to revisit the fundamental concepts of coherence and sequential consistency, which change in this setting. In particular, we show that adding a memory barrier between each instruction does not restore sequential consistency.We go on to extend the C/C++11 model to support non-atomic mixed-size memory accesses, and prove the standard compilation scheme from C11 atomics to POWER remains sound.This is a necessary step towards semantics for real-world shared-memory concurrent code, beyond litmus tests.
Flur , S , Sarkar , S , Pulte , C , Nienhuis , K , Maranget , L , Gray , K , Sezgin , A , Batty , M & Sewell , P 2017 , Mixed-size Concurrency: ARM, POWER, C/C++11, and SC . in Proceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages . ACM , pp. 429-442 , POPL'17 44th ACM SIGPLAN Symposium on Principles of Programming Languages , Paris , France , 15-21 January . DOI: 10.1145/3009837.3009839conference
Proceedings of the 44th annual ACM-SIGPLAN Symposium on Principles of programming languages
© 2016, the Author(s). This work has been made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at dl.acm.org / https://doi.org/10.1145/3009837.3009839
This work was partly funded by the EPSRC Programme Grant REMS: Rigorous Engineering for Mainstream Systems, EP/K008528/1, EPSRC grant C3: Scalable & Verified Shared Memory via Consistency-directed Cache Coherence EP/M027317/1 (Sarkar), an ARM iCASE award (Pulte), a Gates Cambridge Scholarship (Nienhuis). and ANR grant WMC (ANR-11-JS02-011, Maranget).
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