Compound memory models
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Today’s mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but also GPUs and other accelerators. Such heterogeneous processors are starting to expose a shared memory interface across these devices. Given that each of these individual devices typically support a distinct instruction set architecture and a distinct memory consistency model, it is not clear what the memory consistency model of the heterogeneous machine should be. In this paper, we answer this question by formalizing “compound” consistency models: we present a compositional operational model describing the resulting model when devices with distinct consistency models are fused together. We instantiate our model with the compound x86TSO/PTX model – a CPU enforcing x86TSO and a GPU enforcing the PTX model. A key result is that the x86TSO/PTX compound model retains compiler mappings from the language-based (scoped) C memory model. This means that threads mapped to the x86TSO device can continue to use the already proven C-to-x86TSO compiler mapping, and the same for PTX.
Goens , A , Chakraborty , S , Sarkar , S , Agarwal , S , Oswald , N & Nagarajan , V 2023 , ' Compound memory models ' , Proceedings of the ACM on Programming Languages , vol. 7 , no. PLDI , 153 . https://doi.org/10.1145/3591267
Proceedings of the ACM on Programming Languages
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DescriptionFunding: This work was funded by the Engineering and Physical Sciences Research Council, through grant references EP/V038699/1 and EP/V028154/1. Submitted to PLDI 2023, which will publish accepted papers in the Proceedings of the ACM in Programming Languages (PACMPL).
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