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dc.contributor.authorGray, Kathryn
dc.contributor.authorKerneis, Gabriel
dc.contributor.authorMulligan, Dominic
dc.contributor.authorPulte, Christopher
dc.contributor.authorSarkar, Susmit
dc.contributor.authorSewell, Peter
dc.date.accessioned2016-03-18T16:30:06Z
dc.date.available2016-03-18T16:30:06Z
dc.date.issued2015-12-05
dc.identifier.citationGray , K , Kerneis , G , Mulligan , D , Pulte , C , Sarkar , S & Sewell , P 2015 , An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors . in MICRO-48 Proceedings of the 48th International Symposium on Microarchitecture . ACM , New York , pp. 635-646 , The 48th International Symposium on Microarchitecture, 2015 MICRO-48 , Waikiki, Hawaii , United States , 5/12/15 . https://doi.org/10.1145/2830772.2830775en
dc.identifier.citationconferenceen
dc.identifier.isbn9781450340342
dc.identifier.otherPURE: 214242919
dc.identifier.otherPURE UUID: 1c49d9c8-57ab-4470-85aa-052883693be1
dc.identifier.otherScopus: 84959899707
dc.identifier.otherWOS: 000393287300051
dc.identifier.urihttp://hdl.handle.net/10023/8438
dc.descriptionFunding: Scottish Funding Council (SICSA Early Career Industry Fellowship)en
dc.description.abstractWeakly consistent multiprocessors such as ARM and IBM POWER have been with us for decades, but their subtle programmer-visible concurrency behaviour remains challenging, both to implement and to use; the traditional architecture documentation, with its mix of prose and pseudocode, leaves much unclear. In this paper we show how a precise architectural envelope model for such architectures can be defined, taking IBM POWER as our example. Our model specifies, for an arbitrary test program, the set of all its allowable executions, not just those of some particular implementation. The model integrates an operational concurrency model with an ISA model for the fixedpoint non-vector user-mode instruction set (largely automatically derived from the vendor pseudocode, and expressed in a new ISA description language). The key question is the interface between these two: allowing all the required concurrency behaviour, without overcommitting to some particular microarchitectural implementation, requires a novel abstract structure. Our model is expressed in a mathematically rigorous language that can be automatically translated to an executable test-oracle tool; this lets one either interactively explore or exhaustively compute the set of all allowed behaviours of intricate test cases, to provide a reference for hardware and software development.
dc.language.isoeng
dc.publisherACM
dc.relation.ispartofMICRO-48 Proceedings of the 48th International Symposium on Microarchitectureen
dc.rights© 2015, Publisher / the Author(s). This work is made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at dl.acm.org / https://dx.doi.org/10.1145/2830772.2830775en
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectNDASen
dc.subject.lccQA75en
dc.titleAn integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessorsen
dc.typeConference itemen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.identifier.doihttps://doi.org/10.1145/2830772.2830775


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