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dc.contributor.authorFlur, Shaked
dc.contributor.authorGray, Kathryn
dc.contributor.authorPulte, Christopher
dc.contributor.authorSarkar, Susmit
dc.contributor.authorSezgin, Ali
dc.contributor.authorMaranget, Luc
dc.contributor.authorDeacon, Will
dc.contributor.authorSewell, Peter
dc.contributor.editorGill, Andy
dc.identifier.citationFlur , S , Gray , K , Pulte , C , Sarkar , S , Sezgin , A , Maranget , L , Deacon , W & Sewell , P 2016 , Modelling the ARMv8 architecture, operationally : concurrency and ISA . in A Gill (ed.) , Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL '16) . ACM SIGPLAN Notices , no. 1 , vol. 51 , ACM , New York , pp. 608-621 , POPL '16 The 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages , St Petersburg, Florida , United States , 20/01/16 .
dc.identifier.otherORCID: /0000-0002-4259-9213/work/125727591
dc.descriptionThis work was partly funded by the EPSRC Programme Grant REMS: Rigorous Engineering for Mainstream Systems, EP/K008528/1, the Scottish Funding Council (SICSA Early Career Industry Fellowship, Sarkar), an ARM iCASE award (Pulte), and ANR grant WMC (ANR-11-JS02-011, Maranget).en
dc.description.abstractIn this paper we develop semantics for key aspects of the ARMv8 multiprocessor architecture: the concurrency model and much of the 64-bit application-level instruction set (ISA). Our goal is to clarify what the range of architecturally allowable behaviour is, and thereby to support future work on formal verification, analysis, and testing of concurrent ARM software and hardware.Establishing such models with high confidence is intrinsically difficult: it involves capturing the vendor's architectural intent, aspects of which (especially for concurrency) have not previously been precisely defined. We therefore first develop a concurrency model with a microarchitectural flavour, abstracting from many hardware implementation concerns but still close to hardware-designer intuition. This means it can be discussed in detail with ARM architects. We then develop a more abstract model, better suited for use as an architectural specification, which we prove sound w.r.t.~the first. The instruction semantics involves further difficulties, handling the mass of detail and the subtle intensional information required to interface to the concurrency model. We have a novel ISA description language, with a lightweight dependent type system, letting us do both with a rather direct representation of the ARM reference manual instruction descriptions. We build a tool from the combined semantics that lets one explore, either interactively or exhaustively, the full range of architecturally allowed behaviour, for litmus tests and (small) ELF executables. We prove correctness of some optimisations needed for tool performance.We validate the models by discussion with ARM staff, and by comparison against ARM hardware behaviour, for ISA single- instruction tests and concurrent litmus tests.
dc.relation.ispartofProceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages (POPL '16)en
dc.relation.ispartofseriesACM SIGPLAN Noticesen
dc.subjectRelaxed Memory Modelsen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.titleModelling the ARMv8 architecture, operationally : concurrency and ISAen
dc.typeConference itemen
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen

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