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The hardware accelerator debate : a financial risk case study using many-core computing
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dc.contributor.author | Varghese, Blesson | |
dc.date.accessioned | 2015-03-17T11:01:09Z | |
dc.date.available | 2015-03-17T11:01:09Z | |
dc.date.issued | 2015-08 | |
dc.identifier.citation | Varghese , B 2015 , ' The hardware accelerator debate : a financial risk case study using many-core computing ' , Computers & Electrical Engineering , vol. 46 , pp. 157-175 . https://doi.org/10.1016/j.compeleceng.2015.01.012 | en |
dc.identifier.other | PURE: 173579965 | |
dc.identifier.other | PURE UUID: 76e1984b-195e-4188-b636-c9c781a0ab90 | |
dc.identifier.other | Scopus: 84924034069 | |
dc.identifier.other | WOS: 000367122800013 | |
dc.identifier.uri | https://hdl.handle.net/10023/6251 | |
dc.description.abstract | The risk of reinsurance portfolios covering globally occurring natural catastrophes, such as earthquakes and hurricanes, is quantified by employing simulations. These simulations are computationally intensive and require large amounts of data to be processed. The use of many-core hardware accelerators, such as the Intel Xeon Phi and the NVIDIA Graphics Processing Unit (GPU), are desirable for achieving high-performance risk analytics. In this paper, we set out to investigate how accelerators can be employed in risk analytics, focusing on developing parallel algorithms for Aggregate Risk Analysis, a simulation which computes the Probable Maximum Loss of a portfolio taking both primary and secondary uncertainties into account. The key result is that both hardware accelerators are useful in different contexts; without taking data transfer times into account the Phi had lowest execution times when used independently and the GPU along with a host in a hybrid platform yielded best performance. | |
dc.language.iso | eng | |
dc.relation.ispartof | Computers & Electrical Engineering | en |
dc.rights | Copyright 2015 Elsevier Ltd. All rights reserved. This is the author’s version of a work that was accepted for publication in Computers & Electrical Engineering. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Computers & Electrical Engineering, 7 February 2015 DOI 10.1016/j.compeleceng.2015.01.012 | en |
dc.subject | Hardware accelerators | en |
dc.subject | Many-core computing | en |
dc.subject | Secondary uncertainty | en |
dc.subject | Financial risk | en |
dc.subject | Catastrophic risk | en |
dc.subject | Risk analysis | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject | NDAS | en |
dc.subject.lcc | QA75 | en |
dc.title | The hardware accelerator debate : a financial risk case study using many-core computing | en |
dc.type | Journal article | en |
dc.description.version | Postprint | en |
dc.contributor.institution | University of St Andrews. School of Computer Science | en |
dc.identifier.doi | https://doi.org/10.1016/j.compeleceng.2015.01.012 | |
dc.description.status | Peer reviewed | en |
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