Show simple item record

Files in this item

Thumbnail

Item metadata

dc.contributor.authorVarghese, Blesson
dc.date.accessioned2015-03-17T11:01:09Z
dc.date.available2015-03-17T11:01:09Z
dc.date.issued2015-08
dc.identifier.citationVarghese , B 2015 , ' The hardware accelerator debate : a financial risk case study using many-core computing ' , Computers & Electrical Engineering , vol. 46 , pp. 157-175 . https://doi.org/10.1016/j.compeleceng.2015.01.012en
dc.identifier.otherPURE: 173579965
dc.identifier.otherPURE UUID: 76e1984b-195e-4188-b636-c9c781a0ab90
dc.identifier.otherScopus: 84924034069
dc.identifier.otherWOS: 000367122800013
dc.identifier.urihttp://hdl.handle.net/10023/6251
dc.description.abstractThe risk of reinsurance portfolios covering globally occurring natural catastrophes, such as earthquakes and hurricanes, is quantified by employing simulations. These simulations are computationally intensive and require large amounts of data to be processed. The use of many-core hardware accelerators, such as the Intel Xeon Phi and the NVIDIA Graphics Processing Unit (GPU), are desirable for achieving high-performance risk analytics. In this paper, we set out to investigate how accelerators can be employed in risk analytics, focusing on developing parallel algorithms for Aggregate Risk Analysis, a simulation which computes the Probable Maximum Loss of a portfolio taking both primary and secondary uncertainties into account. The key result is that both hardware accelerators are useful in different contexts; without taking data transfer times into account the Phi had lowest execution times when used independently and the GPU along with a host in a hybrid platform yielded best performance.
dc.language.isoeng
dc.relation.ispartofComputers & Electrical Engineeringen
dc.rightsCopyright 2015 Elsevier Ltd. All rights reserved. This is the author’s version of a work that was accepted for publication in Computers & Electrical Engineering. Changes resulting from the publishing process, such as peer review, editing, corrections, structural formatting, and other quality control mechanisms may not be reflected in this document. Changes may have been made to this work since it was submitted for publication. A definitive version was subsequently published in Computers & Electrical Engineering, 7 February 2015 DOI 10.1016/j.compeleceng.2015.01.012en
dc.subjectHardware acceleratorsen
dc.subjectMany-core computingen
dc.subjectSecondary uncertaintyen
dc.subjectFinancial risken
dc.subjectCatastrophic risken
dc.subjectRisk analysisen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectNDASen
dc.subject.lccQA75en
dc.titleThe hardware accelerator debate : a financial risk case study using many-core computingen
dc.typeJournal articleen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.identifier.doihttps://doi.org/10.1016/j.compeleceng.2015.01.012
dc.description.statusPeer revieweden


This item appears in the following Collection(s)

Show simple item record