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Risotto : a dynamic binary translator for weak memory model architectures
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dc.contributor.author | Gouicem, Redha | |
dc.contributor.author | Sprokholt, Dennis | |
dc.contributor.author | Ruehl, Jasper | |
dc.contributor.author | Rocha, Rodrigo | |
dc.contributor.author | Spink, Tom | |
dc.contributor.author | Chakraborty, Soham | |
dc.contributor.author | Bhatotia, Pramod | |
dc.contributor.editor | Aamodt, Tor M. | |
dc.contributor.editor | Jerger, Natalie Enright | |
dc.contributor.editor | Swift, Michael | |
dc.date.accessioned | 2023-01-06T16:30:04Z | |
dc.date.available | 2023-01-06T16:30:04Z | |
dc.date.issued | 2022-12-21 | |
dc.identifier.citation | Gouicem , R , Sprokholt , D , Ruehl , J , Rocha , R , Spink , T , Chakraborty , S & Bhatotia , P 2022 , Risotto : a dynamic binary translator for weak memory model architectures . in T M Aamodt , N E Jerger & M Swift (eds) , Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 (ASPLOS 2023) . vol. 1 , ACM , New York, NY , pp. 107–122 , 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2023) , Vancouver , Canada , 25/03/23 . https://doi.org/10.1145/3567955.3567962 | en |
dc.identifier.citation | conference | en |
dc.identifier.isbn | 9781450399159 | |
dc.identifier.other | PURE: 280203289 | |
dc.identifier.other | PURE UUID: cec99969-66ae-4adc-984a-e47c414588c7 | |
dc.identifier.other | ORCID: /0000-0002-7662-3146/work/125303037 | |
dc.identifier.other | Scopus: 85145576440 | |
dc.identifier.uri | http://hdl.handle.net/10023/26704 | |
dc.description.abstract | Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of unmodified binaries. However, DBT systems face correctness and performance challenges, when emulating concurrent binaries from strong to weak memory consistency architectures. As a matter of fact, we report several translation errors in QEMU, when emulating x86 binaries on Arm hosts. To address these challenges, we propose an end-to-end approach that provides correct and efficient emulation for weak memory model architectures. Our contributions are twofold: First, we formalize QEMU’s intermediate representation’s memory model, and use it to propose formally verified mapping schemes to bridge the strong-on-weak memory consistency mismatch. Second, we implement these verified mappings in Risotto, a QEMU-based DBT system that optimizes memory fence placement while ensuring correctness. Risotto further improves performance via cross-architecture dynamic linking of native shared libraries and faster yet correct translation of compare-and-swap operations. We evaluate Risotto using multi-threaded benchmark suites and real-world applications, and show that Risotto improves the emulation performance by 6.7% on average over “erroneous” QEMU, while ensuring correctness. | |
dc.format.extent | 16 | |
dc.language.iso | eng | |
dc.publisher | ACM | |
dc.relation.ispartof | Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1 (ASPLOS 2023) | en |
dc.rights | Copyright © 2022 ACM. This work has been made available online in accordance with publisher policies or with permission. Permission for further reuse of this content should be sought from the publisher or the rights holder. This is the author created accepted manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available athttps://doi.org/10.1145/3567955.3567962 | en |
dc.subject | Binary translation | en |
dc.subject | Memory models | en |
dc.subject | Formal verification | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject | QA76 Computer software | en |
dc.subject | DAS | en |
dc.subject | AC | en |
dc.subject | NIS | en |
dc.subject | MCC | en |
dc.subject.lcc | QA75 | en |
dc.subject.lcc | QA76 | en |
dc.title | Risotto : a dynamic binary translator for weak memory model architectures | en |
dc.type | Conference item | en |
dc.description.version | Postprint | en |
dc.contributor.institution | University of St Andrews. School of Computer Science | en |
dc.identifier.doi | https://doi.org/10.1145/3567955.3567962 | |
dc.date.embargoedUntil | 2022-12-21 |
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