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dc.contributor.authorSilveira, J.
dc.contributor.authorCadore, A.
dc.contributor.authorBarroso, G.
dc.contributor.authorMarcon, C.
dc.contributor.authorWebber, T.
dc.contributor.authorCzekster, R.
dc.date.accessioned2021-05-14T10:30:02Z
dc.date.available2021-05-14T10:30:02Z
dc.date.issued2016-08-01
dc.identifier.citationSilveira , J , Cadore , A , Barroso , G , Marcon , C , Webber , T & Czekster , R 2016 , ' Accurate model for network-on-chip performance evaluation based on timed colored petri net ' , Journal of Integrated Circuits and Systems , vol. 11 , no. 2 , pp. 75-85 . https://doi.org/10.29292/jics.v11i2.432en
dc.identifier.issn1807-1953
dc.identifier.otherPURE: 273265779
dc.identifier.otherPURE UUID: df8ef8d0-33fe-4237-a6f7-36675359bc35
dc.identifier.otherScopus: 85007453889
dc.identifier.otherORCID: /0000-0002-8091-6021/work/90568144
dc.identifier.urihttp://hdl.handle.net/10023/23189
dc.description.abstractNetwork-on-Chip (NoC) is a power architecture that emerged to solve communication issues present in modern Systems-on-Chip (SoCs). NoC based architectures are very scalable and offer high levels of communication parallelism, among other features. Every efficient NoC implementation requires several design steps to accomplish indices of performance. Although there are many system level models, high-level models for NoC are representative in the context of design since they provide fast and accurate analysis, with low modeling effort, for further VHDL implementations. This work proposes a NoC model based on a Timed Colored Petri Net (TCPN) that computes performance indices seamlessly. Network latency and buffer occupation are of special interest in our approach as they represent the key indices when assessing NoC performance. As results, we have validated and refined the model of a 5×5 mesh NoC comparing its indices with equivalent VHDL RTL description under synthetic and real traffic situations. The proposed model is capable of analyzing the influence of the router service time on the average latency time, enabling internal NoC evaluation to optimize buffer length. Simulation results demonstrate the model suitability for latency evaluation with time estimation errors often below 1%. Furthermore, this paper discusses the effort required to extend the model with other NoC architectural features. We conclude that the use of a TCPN model of NoC generates accurate results providing as much detailed information as their equivalent experiments using VHDL description.
dc.format.extent11
dc.language.isoeng
dc.relation.ispartofJournal of Integrated Circuits and Systemsen
dc.rightsCopyright © 2016 Journal of Integrated Circuits and Systems. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.en
dc.subjectColored petri neten
dc.subjectNetwork-on-chipen
dc.subjectPerformance evaluationen
dc.subjectSystem-on-chipen
dc.subjectTK Electrical engineering. Electronics Nuclear engineeringen
dc.subjectElectrical and Electronic Engineeringen
dc.subject.lccTKen
dc.titleAccurate model for network-on-chip performance evaluation based on timed colored petri neten
dc.typeJournal articleen
dc.description.versionPublisher PDFen
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.identifier.doihttps://doi.org/10.29292/jics.v11i2.432
dc.description.statusPeer revieweden


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