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dc.contributor.authorYu, Teng
dc.contributor.authorPetoumenos, Pavlos
dc.contributor.authorJanjic, Vladimir
dc.contributor.authorLeather, Hugh
dc.contributor.authorThomson, John Donald
dc.contributor.editorMars, Jason
dc.contributor.editorTang, Lingjia
dc.contributor.editorXue, Jingling
dc.contributor.editorWu, Peng
dc.date.accessioned2020-02-22T00:33:11Z
dc.date.available2020-02-22T00:33:11Z
dc.date.issued2020-02-22
dc.identifier.citationYu , T , Petoumenos , P , Janjic , V , Leather , H & Thomson , J D 2020 , COLAB : a collaborative multi-factor scheduler for asymmetric multicore processors . in J Mars , L Tang , J Xue & P Wu (eds) , Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization (GCO 2020) . International Symposium on Code Generation and Optimization , ACM , New York , pp. 268-279 , International Symposium on Code Generation and Optimization (CGO 2020) , San Diego , California , United States , 22/02/20 . https://doi.org/10.1145/3368826.3377915en
dc.identifier.citationconferenceen
dc.identifier.isbn9781450370479
dc.identifier.issn1931-0544
dc.identifier.otherPURE: 265419894
dc.identifier.otherPURE UUID: 2d91dc53-76fe-406d-a74a-fc56acc0dafd
dc.identifier.otherScopus: 85082110482
dc.identifier.otherWOS: 000613250200021
dc.identifier.urihttp://hdl.handle.net/10023/19514
dc.descriptionFunding: Partially funded by the UK EPSRC grants Discovery: Pattern Discovery and Program Shaping for Many-core Systems (EP/P020631/1) and ABC: Adaptive Brokerage for Cloud (EP/R010528/1); Royal Academy of Engineering under the Research Fellowship scheme.en
dc.description.abstractIncreasingly prevalent asymmetric multicore processors (AMP) are necessary for delivering performance in the era of limited power budget and dark silicon. However, the software fails to use them efficiently. OS schedulers, in particular, handle asymmetry only under restricted scenarios. We have efficient symmetric schedulers, efficient asymmetric schedulers for single-threaded workloads, and efficient asymmetric schedulers for single program workloads. What we do not have is a scheduler that can handle all runtime factors affecting AMP for multi-threaded multi-programmed workloads. This paper introduces the first general purpose asymmetry-aware scheduler for multi-threaded multi-programmed workloads. It estimates the performance of each thread on each type of core and identifies communication patterns and bottleneck threads. The scheduler then makes coordinated core assignment and thread selection decisions that still provide each application its fair share of the processor's time. We evaluate our approach using the GEM5 simulator on four distinct big.LITTLE configurations and 26 mixed workloads composed of PARSEC and SPLASH2 benchmarks. Compared to the state-of-the art Linux CFS and AMP-aware schedulers, we demonstrate performance gains of up to 25% and 5% to 15% on average depending on the hardware setup.
dc.language.isoeng
dc.publisherACM
dc.relation.ispartofProceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization (GCO 2020)en
dc.relation.ispartofseriesInternational Symposium on Code Generation and Optimizationen
dc.rightsCopyright © 2020 Association for Computing Machinery. This work has been made available online in accordance with publisher policies or with permission. Permission for further reuse of this content should be sought from the publisher or the rights holder. This is the author created accepted manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at https://doi.org/10.1145/3368826.3377915en
dc.subjectAsymmetric multicore processoren
dc.subjectOS scheduleren
dc.subjectMulti-threaded multi-programmed workloadsen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subjectQA76 Computer softwareen
dc.subjectNDASen
dc.subjectBDCen
dc.subjectR2Cen
dc.subject~DC~en
dc.subject.lccQA75en
dc.subject.lccQA76en
dc.titleCOLAB : a collaborative multi-factor scheduler for asymmetric multicore processorsen
dc.typeConference itemen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.identifier.doihttps://doi.org/10.1145/3368826.3377915
dc.date.embargoedUntil2020-02-22


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