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High-level programming for heterogeneous and hierarchical parallel systems

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dc.contributor.authorGarcía-Blas, Javier
dc.contributor.authorBrown, Christopher
dc.date.accessioned2019-11-14T00:36:34Z
dc.date.available2019-11-14T00:36:34Z
dc.date.issued2018-11-14
dc.identifier.citationGarcía-Blas , J & Brown , C 2018 , ' High-level programming for heterogeneous and hierarchical parallel systems ' , International Journal of High Performance Computing Applications , vol. 32 , no. 6 , pp. 804-806 . https://doi.org/10.1177/1094342018807840en
dc.identifier.issn1094-3420
dc.identifier.otherPURE: 256640850
dc.identifier.otherPURE UUID: d89e7101-54dd-407f-b2c4-22c6ff38391b
dc.identifier.othercrossref: 10.1177/1094342018807840
dc.identifier.otherScopus: 85056795359
dc.identifier.otherWOS: 000450291400004
dc.identifier.otherORCID: /0000-0001-6030-2885/work/70619182
dc.identifier.urihttps://hdl.handle.net/10023/18917
dc.description.abstractHigh-Level Heterogeneous and Hierarchical Parallel Systems (HLPGPU) aims to bring together researchers and practitioners to present new results and ongoing work on those aspects of high-level programming relevant, or specific to general-purpose computing on graphics processing units (GPGPUs) and new architectures. The 2016 HLPGPU symposium was an event co-located with the HiPEAC conference in Prague, Czech Republic. HLPGPU is targeted at high-level parallel techniques, including programming models, libraries and languages, algorithmic skeletons, refactoring tools and techniques for parallel patterns, tools and systems to aid parallel programming, heterogeneous computing, timing analysis and statistical performance models.
dc.language.isoeng
dc.relation.ispartofInternational Journal of High Performance Computing Applicationsen
dc.rights© 2018, the Author(s). This work has been made available online in accordance with the publisher's policies. This is the author created accepted version manuscript following peer review and as such may differ slightly from the final published version. The final published version of this work is available at https://doi.org/10.1177/1094342018807840en
dc.subjectGPGPUen
dc.subjectHeterogeneousen
dc.subjectDomain-specific parallel patternsen
dc.subjectPerformanceen
dc.subjectProgramming modelsen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.subject.lccQA75en
dc.titleHigh-level programming for heterogeneous and hierarchical parallel systemsen
dc.typeJournal itemen
dc.description.versionPostprinten
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen
dc.identifier.doihttps://doi.org/10.1177/1094342018807840
dc.description.statusPeer revieweden
dc.date.embargoedUntil2019-11-14


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