Show simple item record

Files in this item


Item metadata

dc.contributor.authorBofill, Miquel
dc.contributor.authorEspasa, Joan
dc.contributor.authorVillaret, Mateu
dc.identifier.citationBofill , M , Espasa , J & Villaret , M 2019 , ' Relaxing non-interference requirements in parallel plans ' , Logic Journal of the IGPL , vol. 29 , no. 1 , pp. 45–71 .
dc.identifier.otherPURE: 261776815
dc.identifier.otherPURE UUID: ef444f33-9503-4b5b-93cb-e1434be430b6
dc.identifier.othercrossref: 10.1093/jigpal/jzz026
dc.identifier.otherWOS: 000637315900004
dc.identifier.otherScopus: 85104952773
dc.descriptionFunding: UK EPSRC (EP/P015638/1).en
dc.description.abstractThe aim of being able to reason about quantities, time or space has been the main objective of the many efforts on the integration of propositional planning with extensions to handle different theories. Planning modulo theories (PMTs) are an approximation inspired by satisfiability modulo theories (SMTs) that generalize the integration of arbitrary theories with propositional planning. Parallel plans are crucial to reduce plan lengths and hence the time needed to reach a feasible plan in many approaches. Parallelization of actions relies on the notion of (non-)interference, which is usually determined syntactically at compile time. In this paper we define a semantic notion of interference between actions in PMT. Apart from being strictly stronger than any syntactic notion of interference, we show how semantic interference can be easily and efficiently checked by calling an off-the-shelf SMT solver at compile time, constituting a technique orthogonal to the solving method.
dc.relation.ispartofLogic Journal of the IGPLen
dc.rights© The Author(s) 2019. Published by Oxford University Press. This is an Open Access article distributed under the terms of the Creative Commons Attribution License (, which permits unrestricted reuse, distribution, and reproduction in any medium, provided the original work is properly cited.en
dc.subjectPlanning modulo theoriesen
dc.subjectPlanning as satisfiabilityen
dc.subjectParallel plansen
dc.subjectBC Logicen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.titleRelaxing non-interference requirements in parallel plansen
dc.typeJournal articleen
dc.description.versionPublisher PDFen
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.description.statusPeer revieweden

This item appears in the following Collection(s)

Show simple item record