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POSTER : A collaborative multi-factor scheduler for asymmetric multicore processors
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dc.contributor.author | Yu, Teng | |
dc.contributor.author | Petoumenos, Pavlos | |
dc.contributor.author | Janjic, Vladimir | |
dc.contributor.author | Zhu, Mingcan | |
dc.contributor.author | Leather, Hugh | |
dc.contributor.author | Thomson, John Donald | |
dc.date.accessioned | 2019-10-03T09:30:01Z | |
dc.date.available | 2019-10-03T09:30:01Z | |
dc.date.issued | 2019-11-07 | |
dc.identifier.citation | Yu , T , Petoumenos , P , Janjic , V , Zhu , M , Leather , H & Thomson , J D 2019 , POSTER : A collaborative multi-factor scheduler for asymmetric multicore processors . in Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019) . , 8891662 , International Conference on Parallel Architectures and Compilation Techniques , IEEE Computer Society , pp. 486-487 , 28th International Conference on Parallel Architectures and Compilation Techniques , Seattle , Washington , United States , 21/09/19 . https://doi.org/10.1109/PACT.2019.00058 | en |
dc.identifier.citation | conference | en |
dc.identifier.isbn | 9781728136141 | |
dc.identifier.isbn | 9781728136134 | |
dc.identifier.issn | 1089-795X | |
dc.identifier.other | PURE: 261471155 | |
dc.identifier.other | PURE UUID: 309e61b1-83fd-46cc-978c-32da00fe9ec4 | |
dc.identifier.other | Scopus: 85075446054 | |
dc.identifier.other | WOS: 000550990200050 | |
dc.identifier.uri | https://hdl.handle.net/10023/18604 | |
dc.description.abstract | Asymmetric multicore processors (AMP) are necessary for extracting performance in an era of limited power budget and dark silicon. We have efficient symmetric schedulers, efficient asymmetric schedulers for single-threaded workloads, and efficient asymmetric schedulers for single program workloads. What we do not have is a scheduler that can handle all three factors affecting AMP scheduling: core affinity, thread criticality, and scheduling fairness. To address this problem, this paper introduces the first general purpose asymmetry-aware scheduler targeting multi-threaded multi-programmed workloads. It estimates the performance of each thread on each type of core and it identifies communication patterns and bottleneck threads. With this information, the scheduler makes coordinated core assignment and thread selection decisions that still provide each application its fair share of the processor's time. We evaluated our approach on GEM5 through four distinct big.LITTLE configurations and multi-threaded multi-programmed workloads composed of PARSEC and SPLASH2 benchmarks. Compared against the Linux CFS scheduler and a state-of-the-art AMP-aware scheduler, we demonstrate performance gains of up to 25% and 5% to 15% on average depending on the hardware setup. | |
dc.format.extent | 2 | |
dc.language.iso | eng | |
dc.publisher | IEEE Computer Society | |
dc.relation.ispartof | Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019) | en |
dc.relation.ispartofseries | International Conference on Parallel Architectures and Compilation Techniques | en |
dc.rights | Copyright © 2019 IEEE. This work has been made available online in accordance with publisher policies or with permission. Permission for further reuse of this content should be sought from the publisher or the rights holder. This is the author created accepted manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at https://doi.org/10.1109/PACT.2019.00058 | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject | NS | en |
dc.subject.lcc | QA75 | en |
dc.title | POSTER : A collaborative multi-factor scheduler for asymmetric multicore processors | en |
dc.type | Conference item | en |
dc.description.version | Postprint | en |
dc.contributor.institution | University of St Andrews. School of Computer Science | en |
dc.identifier.doi | https://doi.org/10.1109/PACT.2019.00058 |
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