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dc.contributor.authorChasparis, Georgios
dc.contributor.authorRossbory, Michael
dc.contributor.authorJanjic, Vladimir
dc.contributor.authorHammond, Kevin
dc.identifier.citationChasparis , G , Rossbory , M , Janjic , V & Hammond , K 2019 , Learning-based dynamic pinning of parallelized applications in many-core systems . in Proceedings 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2019) . , 8671569 , Institute of Electrical and Electronics Engineers Inc. , 27th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP) , Pavia , Italy , 13/02/19 .
dc.identifier.otherPURE: 259528503
dc.identifier.otherPURE UUID: 4788e1bd-2428-43e7-b7e0-9faf34fc87ee
dc.identifier.otherScopus: 85063880618
dc.identifier.otherORCID: /0000-0002-4326-4562/work/59464564
dc.identifier.otherWOS: 000467257000001
dc.descriptionFunding: This work has been supported by the European Union grant EU H2020-ICT-2014-1 project RePhrase (No. 644235). It has also been partially supported by the Austrian Ministry for Transport, Innovation and Technology, the Federal Ministry of Science, Research and Economy, and the Province of Upper Austria in the frame of the COMET center SCCH.en
dc.description.abstractThis paper introduces a learning-based framework for dynamic placement of threads of parallel applications to the cores of Non-Uniform Memory Access (NUMA) architectures. Adaptation takes place in two levels, where at the first level each thread independently decides on which group of cores (NUMA node) it will execute, and on the second level it decides to which particular core from the group it will be pinned. Naturally, these two adaptation levels run on different time-scales: a low-frequency switching for the NUMA-node adaptation, and a high-frequency switching for the CPU-node level adaptation. In addition, the learning dynamics have been designed to handle measurement noise and rapid variations in the performance of the threads. The advantage of the proposed learning scheme is the ability to easily incorporate any multi-objective criterion and easily adapt to performance variations during runtime. Our objective is to demonstrate that this framework is appropriate for supervising parallel processes and intervening with respect to better resource allocation. Under the multi-objective criterion of maximizing total completed instructions per second (i.e., both computational and memory-access instructions), we compare the performance of the proposed scheme with the Linux operating system scheduler. We have observed that performance improvement could be significant especially under limited availability of resources and under irregular memory-access patterns.
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relation.ispartofProceedings 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2019)en
dc.rights© 2019, IEEE. This work has been made available online in accordance with the publisher's policies. This is the author created accepted version manuscript following peer review and as such may differ slightly from the final published version. The final published version of this work is available at
dc.subjectQA75 Electronic computers. Computer scienceen
dc.titleLearning-based dynamic pinning of parallelized applications in many-core systemsen
dc.typeConference itemen
dc.contributor.institutionUniversity of St Andrews.School of Computer Scienceen
dc.contributor.institutionUniversity of St Andrews.Centre for Interdisciplinary Research in Computational Algebraen

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