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Lattice-based scheduling for multi-FPGA systems
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dc.contributor.author | Yu, Teng | |
dc.contributor.author | Feng, Bo | |
dc.contributor.author | Stillwell, Mark | |
dc.contributor.author | Guo, Liucheng | |
dc.contributor.author | Ma, Yuchun | |
dc.contributor.author | Thomson, John Donald | |
dc.date.accessioned | 2018-12-20T12:30:04Z | |
dc.date.available | 2018-12-20T12:30:04Z | |
dc.date.issued | 2018-12-10 | |
dc.identifier.citation | Yu , T , Feng , B , Stillwell , M , Guo , L , Ma , Y & Thomson , J D 2018 , Lattice-based scheduling for multi-FPGA systems . in Proceedings of the International Conference on Field-Programmable Technology 2018, Naha, Okinawa, Japan . IEEE Press , International Conference on Field-Programmable Technology (FPT'18) , Naha, Okinawa , Japan , 10/12/18 . | en |
dc.identifier.citation | conference | en |
dc.identifier.other | PURE: 256719143 | |
dc.identifier.other | PURE UUID: 69fde49c-1834-4285-8bba-b9050ae1933a | |
dc.identifier.other | Scopus: 85068335533 | |
dc.identifier.other | WOS: 000491322000055 | |
dc.identifier.uri | https://hdl.handle.net/10023/16738 | |
dc.description.abstract | Accelerators are becoming increasingly prevalent in distributed computation. FPGAs have been shown to be fast and power efficient for particular tasks, yet scheduling on FPGA-based multi-accelerator systems is challenging when workloads vary significantly in granularity in terms of task size and/or number of computational units required. We present a novel approach for dynamically scheduling tasks on networked multi-FPGA systems which maintains high performance, even in the presence of irregular tasks. Our topological ranking-based scheduling allows realistic irregular workloads to be processed while maintaining a significantly higher level of performance than existing schedulers. | |
dc.language.iso | eng | |
dc.publisher | IEEE Press | |
dc.relation.ispartof | Proceedings of the International Conference on Field-Programmable Technology 2018, Naha, Okinawa, Japan | en |
dc.rights | © 2018, IEEE. This work has been made available online in accordance with the publisher’s policies. This is the author created accepted version manuscript following peer review and as such may differ slightly from the final published version. The final published version of this work is available at https://ieeexplore.ieee.org/ | en |
dc.subject | Runtime scheduling | en |
dc.subject | Lattice | en |
dc.subject | Representation | en |
dc.subject | Multi-FPGA | en |
dc.subject | QA75 Electronic computers. Computer science | en |
dc.subject | T Technology | en |
dc.subject | NS | en |
dc.subject.lcc | QA75 | en |
dc.subject.lcc | T | en |
dc.title | Lattice-based scheduling for multi-FPGA systems | en |
dc.type | Conference item | en |
dc.description.version | Postprint | en |
dc.contributor.institution | University of St Andrews. School of Computer Science | en |
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