Show simple item record

Files in this item


Item metadata

dc.contributor.authorPulte, Christopher
dc.contributor.authorFlur, Shaked
dc.contributor.authorDeacon, Will
dc.contributor.authorFrench, Jon
dc.contributor.authorSarkar, Susmit
dc.contributor.authorSewell, Peter
dc.identifier.citationPulte , C , Flur , S , Deacon , W , French , J , Sarkar , S & Sewell , P 2018 , Simplifying ARM concurrency : multicopy-atomic axiomatic and operational models for ARMv8 . in Proceedings of the ACM on Programming Languages (POPL '18) . , 19 , Proceedings of the ACM on Programming Languages , no. POPL , vol. 2 , ACM , New York , pp. 1-29 , POPL '18 45th ACM SIGPLAN Symposium on Principles of Programming Languages , Los Angeles , California , United States , 7/01/18 .
dc.identifier.otherPURE: 251634638
dc.identifier.otherPURE UUID: b90e0329-f3ab-409c-88c2-e88cf753003a
dc.identifier.otherWOS: 000688016900019
dc.identifier.otherScopus: 85120113233
dc.identifier.otherORCID: /0000-0002-4259-9213/work/125727569
dc.description.abstractARM has a relaxed memory model, previously specified in informal prose for ARMv7 and ARMv8. Over time, and partly due to work building formal semantics for ARM concurrency, it has become clear that some of the complexity of the model is not justified by the potential benefits. In particular, the model was originally non-multicopy-atomic: writes could become visible to some other threads before becoming visible to all — but this has not been exploited in production implementations, the corresponding potential hardware optimisations are thought to have insufficient benefits in the ARM context, and it gives rise to subtle complications when combined with other ARMv8 features. The ARMv8 architecture has therefore been revised: it now has a multicopy-atomic model. It has also been simplified in other respects, including more straightforward notions of dependency, and the architecture now includes a formal concurrency model. In this paper we detail these changes and discuss their motivation. We define two formal concurrency models: an operational one, simplifying the Flowing model of Flur et al., and the axiomatic model of the revised ARMv8 specification. The models were developed by an academic group and by ARM staff, respectively, and this extended collaboration partly motivated the above changes. We prove the equivalence of the two models. The operational model is integrated into an executable exploration tool with new web interface, demonstrated by exhaustively checking the possible behaviours of a loop-unrolled version of a Linux kernel lock implementation, a previously known bug due to unprevented speculation, and a fixed version.
dc.relation.ispartofProceedings of the ACM on Programming Languages (POPL '18)en
dc.relation.ispartofseriesProceedings of the ACM on Programming Languagesen
dc.rightsCopyright © 2018, the Author(s). This work has been made available online in accordance with the publisher’s policies. This is the author created, accepted version manuscript following peer review and may differ slightly from the final published version. The final published version of this work is available at
dc.subjectRelaxed Memory Modelsen
dc.subjectQA75 Electronic computers. Computer scienceen
dc.titleSimplifying ARM concurrency : multicopy-atomic axiomatic and operational models for ARMv8en
dc.typeConference itemen
dc.contributor.institutionUniversity of St Andrews. School of Computer Scienceen

This item appears in the following Collection(s)

Show simple item record