Show simple item record

Files in this item

Thumbnail

Item metadata

dc.contributor.advisorThomson, John Donald
dc.contributor.authorYu, Teng
dc.coverage.spatialviii, 174 p.en_US
dc.date.accessioned2020-04-14T07:04:18Z
dc.date.available2020-04-14T07:04:18Z
dc.date.issued2020-06
dc.identifier.urihttp://hdl.handle.net/10023/19797
dc.description.abstractOver the past decade, heterogeneous processors and accelerators have become increasingly prevalent in modern computing systems. Compared with previous homogeneous parallel machines, the hardware heterogeneity in modern systems provides new opportunities and challenges for performance acceleration. Classic operating systems optimisation problems such as task scheduling, and application-specific optimisation techniques such as the adaptive data partitioning of parallel algorithms, are both required to work together to address hardware heterogeneity. Significant effort has been invested in this problem, but either focuses on a specific type of heterogeneous systems or algorithm, or a high-level framework without insight into the difference in heterogeneity between different types of system. A general software framework is required, which can not only be adapted to multiple types of systems and workloads, but is also equipped with the techniques to address a variety of hardware heterogeneity. This thesis presents approaches to design general heterogeneity-aware software frameworks for system performance acceleration. It covers a wide variety of systems, including an OS scheduler targeting on-chip asymmetric multi-core processors (AMPs) on mobile devices, a hierarchical many-core supercomputer and multi-FPGA systems for high performance computing (HPC) centers. Considering heterogeneity from on-chip AMPs, such as thread criticality, core sensitivity, and relative fairness, it suggests a collaborative based approach to co-design the task selector and core allocator on OS scheduler. Considering the typical sources of heterogeneity in HPC systems, such as the memory hierarchy, bandwidth limitations and asymmetric physical connection, it proposes an application-specific automatic data partitioning method for a modern supercomputer, and a topological-ranking heuristic based schedule for a multi-FPGA based reconfigurable cluster. Experiments on both a full system simulator (GEM5) and real systems (Sunway Taihulight Supercomputer and Xilinx Multi-FPGA based clusters) demonstrate the significant advantages of the suggested approaches compared against the state-of-the-art on variety of workloads.en_US
dc.description.sponsorship"This work is supported by St Leonards 7th Century Scholarship and Computer Science PhD funding from University of St Andrews; by UK EPSRC grant Discovery: Pattern Discovery and Program Shaping for Manycore Systems (EP/P020631/1)." -- Acknowledgementsen
dc.language.isoenen_US
dc.publisherUniversity of St Andrews
dc.subjectHeterogeneous systemsen_US
dc.subjectHigh performance computingen_US
dc.subjectSystem softwareen_US
dc.subject.lccQA76.88Y8
dc.subject.lcshHeterogeneous computingen
dc.subject.lcshHigh performance computingen
dc.subject.lcshOperating systems (Computers)en
dc.titleHeterogeneity-aware scheduling and data partitioning for system performance accelerationen_US
dc.typeThesisen_US
dc.contributor.sponsorUniversity of St Andrews. 7th century Scholarshipen_US
dc.contributor.sponsorUniversity of St Andrewsen_US
dc.contributor.sponsorEngineering and Physical Sciences Research Council (EPSRC)en_US
dc.type.qualificationlevelDoctoralen_US
dc.type.qualificationnamePhD Doctor of Philosophyen_US
dc.publisher.institutionThe University of St Andrewsen_US


This item appears in the following Collection(s)

Show simple item record